1. Field of the Invention
The present invention relates to a memory device having a global input/output line, and more particularly to a memory device and a method of operating the same for controlling an operation of a sense amplifier coupled to the global input/output line and controlling a precharge operation of the global input/output line.
2. Description of the Related Art
Generally, a memory device has a hierarchical structure of data input/output lines to read data stored in a memory cell or write data to the memory cell. To allow for continuous transfer of data, the input/output lines are typically precharged to a predetermined voltage level repeatedly during a read or write operation.
FIG. 1 is a block diagram illustrating a conventional memory device having a hierarchical structure of input/output lines.
Referring to FIG. 1, the memory device 100 includes a core area 110 and a peripheral area 120. The core area 110 includes memory cells 111, a bit line pair BL and /BL coupled to the memory cells, a bit line sense amplifier 112 for detecting and amplifying a voltage difference between the bit line pair, a local input/output line pair LIO and /LIO coupled to the bit line pair through a first switching circuit 113 and a global input/output line pair GIO and /GIO coupled to the local input/output pair LIO and /LIO through a second switching circuit 114.
The peripheral area 120 includes a control signal generating unit 121, a precharge circuit 122 for precharging the global input/output line pair GIO and /GIO to a predetermined voltage level, a sense amplifier 123 for detecting and amplifying a voltage difference between the global input/output line pair GIO and /GIO and an output buffer 124.
The control signal generating unit 121 generates a first switching control signal CSL, a second switching control signal SEL, a sense amplifier control signal PIOSE and a precharge control signal PIOPPB for the global input/output line pair in response to a read command RD and an address signal ADDR.
The signal CSL controls a turn-on/off of the first switching circuit 113. The signal SEL controls a turn-on/off of the second switching circuit 114. The signal PIOSE controls enabling or disabling of the sense amplifier 123. The signal PIOPPB controls the precharge circuit 122 to precharge the global input/output line pair GIO and /GIO to a predetermined voltage level.
FIG. 2 is a timing diagram illustrating an operation of a read operation of the memory device in FIG. 1.
Referring to FIGS. 1 and 2, the precharge circuit 122 is enabled by the control signal PIOPPB to precharge the global input/output signal pair GIO and /GIO to a predetermined voltage (e.g., an internal power voltage) before the read command RD and the address ADDR are received. When the read command RD and the address ADDR are received, the PIOPPB signal becomes logic ‘high’ to disable the precharge circuit 122. The signal CSL turns on the first switching circuit 113 in response to the read command RD and the address ADDR so that data on the bit line pair BL and /BL are transferred to the local input/output line pair LIO and /LIO. The signal SEL turns on the second switching circuit 114 so that data on the local input/output line pair LIO and /LIO are transferred to the global input/output line pair GIO and /GIO. When the second switching circuit 114 is turned on, a voltage difference is generated between the global input/output line pair GIO and /GIO.
Ideally, the signal PIOSE is preferred to become a high state to enable the sense amplifier 123 when the sense amplifier 123 can detect the voltage difference (e.g., ΔV in FIG. 2) between the global input/output line pair GIO and /GIO (e.g., at a time point A in FIG. 2). But, in a real embodiment, the signal PIOSE transitions to a high state at a time point B to enable the sense amplifier 123 in consideration of variations in process, voltage, temperature, etc.
In addition, the signal PIOSE transitions to a low state after a sufficient time period Δt to disable the sense amplifier 123 to enable the sense amplifier 123 to completely detect and amplify the potential difference between the global input/output line pair.
The signal PIOPPB transitions to a low state after the sense amplifier 123 is disabled by the signal PIOSE so as to perform a next bursting operation or a corresponding operation in response to the next input command so that the global input/output line pair GIO and /GIO are again precharged to the predetermined voltage level (e.g., an internal power voltage).
Similarly, the signal CSL and the signal SEL respectively transition to a low state to perform a next bursting operation or corresponding operation according to a next command so that the first and second switching circuits are turned off.
However, since the load of the global input/output line pair is increased as the memory has an increased capacity, a time period required for precharging the global input/output line pair is increased. So as to operate the memory having a large capacity at a high speed, the precharging speed of the global input/output pair needs to be increased. In addition, the operating time of the sense amplifier needs to be minimized so as to achieve high-speed operation and low power consumption of the memory device.